1. Field of the Invention
The present invention relates to apparatus and method for driving a display panel, more particularly, to control of a charge pump circuit integrated within a display panel driver. This application claims the benefit of priority based on Japanese Patent Application No. 2006-331972, filed on Dec. 8, 2006, the disclosure of which is incorporated herein by reference.
2. Description of Related Art
LCD (liquid crystal display) panel drivers for cell phones often integrate a charge pump circuit that generates a boosted power supply voltage used for driving a LCD panel. One commonly-used method of controlling a charge pump circuit is pulse skipping which involves enabling and disenabling of a boosting clock supplied to the charge pump circuit in response to the boosted power supply voltage generated. The pulse skipping technique, however, may undesirably cause the generation of ripple on the outputs of the source driver.
In detail, a charge pump circuit adapted to pulse skipping undesirably suffers from more ripple as the increase in the input power supply voltage. The ripple generated by the charge pump circuit undesirably results in ripple on the outputs of the source drive circuit, because of the electromagnetic coupling within power supply lines and input circuits of the source drive circuit. The ripple on the outputs of the source drive circuit undesirably causes display noise observed as horizontal stripes. There is a need for avoiding such display noise.
In the following, an exemplary configuration of the charge pump circuit and the ripple generation therein are discussed in detail.
FIG. 1 shows a circuit diagram illustrating an exemplary configuration of an LCD panel driver incorporating a charge pump booster circuit adapted to pulse skipping. The LCD panel driver includes a booster circuit 8 and a source drive circuit 30. The booster circuit 8 boosts an input power supply voltage VDC supplied thereto to generate a boosted power supply voltage VDC2. The boosted power supply voltage VDC2 is supplied to the source drive circuit 30. As disclosed in Japanese Laid-Open Patent Application No. 2005-278383, the booster circuit 8 typically includes a charge pump circuit 10, voltage dividing resistors R1 and R2, a smoothing capacitor C3, a comparator CMP1, a level shift circuit 14, a NAND circuit 12, and a NOT circuit 11.
The charge pump circuit 10 is provided with a NMOS transistor T11, PMOS transistors T12 to T14 and a boost capacitor C1, so as to achieve voltage doubling through charge pumping. The NMOS transistor T11 has a source earth-grounded and a drain connected to the drain of the transistor T12 and also to one electrode of the boost capacitor C1. The PMOS transistor T12 has a source receiving the power supply voltage VDC. The other electrode of the booster circuit C1 is connected to the drain of the PMOS transistor T13, and also connected to the output of the charge pump circuit 10, on which a boosted power supply voltage VDC2 is generated, through the PMOS transistor T14. The PMOS transistor T13 has a source receiving the power supply voltage VDC. The gates of the transistors T11, T12 and T14 are connected to the output of the NAND circuit 12 and driven by the NAND circuit 12. The output of the NAND circuit 12 is further connected to the gate of the PMOS transistor T13 through the NOT circuit 11.
The smoothing circuit C3 smoothes the boosted power supply voltage VDC2 generated on the output of the charge pump circuit 10. The voltage dividing resistors R1 and R2 are connected in parallel to the smoothing capacitor C3 to generate an output monitor voltage mo through voltage division of the smoothed boosted power supply voltage VDC2. The output monitor voltage mo is fed to the comparator CMP1. The comparator CMP1 compares the output monitor voltage mo with a reference voltage REF1 generated by a BGR (band gap reference) circuit, and outputs an output signal ps in accordance with the comparison result. The output signal ps is set to “L”, when the output monitor voltage mo exceeds the reference voltage REF1; otherwise the output signal ps is set to “H”. The output signal ps is fed to the NAND circuit 12 through the level shift circuit 14 which provides level conversion. The boosted power supply voltage VDC2 can be set to a desired voltage level by adjusting the resistance ratio of the resistors R1 and R2.
The NAND circuit 12 provides the NAND of the comparison result and a boosting clock CLK for the gates of the transistors T11, T12 and T14; the output signal of the NAND circuit 12 is denoted by the symbol “gc” in FIG. 1. When the comparator CMP1 sets the output signal ps to “L” in response to the output monitor voltage mo exceeding the reference voltage REF1, the boosting clock CLK stops being supplied to the charge pump circuit 10, which results in suspending the charge and discharge of the smoothing capacitor C3. When the comparator CMP1 sets the output signal ps to “H” in response to the output monitor voltage mo being equal to or less than the reference voltage REF1, on the other hand, the boosting clock is supplied to the charge pump circuit 10 to allow the charge and discharge of the smoothing capacitor C3.
The boosted power supply voltage VDC2 is fed to the level shift circuit 14, the NOT circuit 11, and the NAND circuit 12 in addition to the source drive circuit 30, while the charge pump circuit 10 and comparator CMP1 operates on the input power supply voltage VDC.
As disclosed in Japanese Laid-Open Patent Application No. JP-A Heisei 5-35211, the source drive circuit 30 is typically provided with a gamma resistor 32, decoder circuits 33 (one shown), source amplifiers 35 (one shown), and switches 37 and 38 (one shown for each). The gamma resistor 32 generates a set of gamma-corrected grayscale voltages. The decoder circuits 33 each select one of the grayscale voltages as indicated by display data. The source amplifiers 35, each comprised of a voltage follower, provide current amplification for the grayscale voltages outputted from the respective decoder circuits 33 to generate drive voltages corresponding to the selected grayscale voltages. The drive voltages are fed to the LCD panel from the source outputs SOUT to drive liquid crystal elements CL (one shown) within selected pixels of the LCD panel. The decoder circuits 33 and the source amplifiers 35 operate on the boosted power supply voltage VDC2 received from the booster circuit 8.
The switches 37 are used to provide electrical connections between the source amplifiers 35 and the source outputs SOUT of the source drive circuit 30, and the switches 38 are used to provide electrical connections between the decoder circuits 33 and the source outputs SOUT.
The source amplifiers 35 and the switches 37 and 38 are controlled by a set of control signals SCA, SCB and SCC which are used for timing control of the image display on the liquid crystal display panel. The control signals SCA, SCB and SCC are allowed to be exclusively set to “H”; any two of control signals SCA, SCB and SCC are not allowed to be set to “H” at the same time.
When the control signal SCA is set to “H” with the control signals SCB and SCC set to “L”, the switches 37 are turned on and the source amplifiers 35 are activated, while the switches 38 are turned off. This allows the source amplifiers 35 to drive the liquid crystal elements CL within the selected pixels. This operation may be refereed to as “source amplifier drive”, hereinafter. Additionally, the period during which the source drive circuit 30 implements the “source amplifier drive” may be referred to as the “source amplifier drive period”.
When the control signal SCB is set to “H” with the control signals SCA and SCC set to “L”, the switches 38 are turned on, while the source amplifiers 35 are deactivated with the switches 37 turned off. The switches 38 provide direct electrical connections between the source outputs SOUT and the outputs of the decoder circuits 33, and this allows the decoder circuits 33 to directly drive the pixels CL. Although having substantially no drive ability, the decoder circuits 33 are designed to provide electrical connections between the source outputs SOUT and the gamma resistor 32 and to thereby maintain the voltage levels of the drive voltages on the source outputs SOUT. Such operation may be referred to as the “gamma resistor direct drive”. Additionally, the period during which the source drive circuit 30 implements the “gamma resistor direct drive” may be referred to as the “gamma resistor direct drive period”. The gamma resistor direct drive effectively reduces the power consumption of the source amplifiers 35.
When the control signal SCC is set to “H” with the control signals SCA and SCB set to “L”, the switches 37 and 38 are turned off and the source amplifiers 35 are deactivated. In this operation, the source outputs SOUT of the source drive circuit 30 are set to high-impedance. The period during which the source drive circuit 30 sets the source outputs SOUT to high-impedance may be referred to as the “high-impedance period”, hereinafter.
Although the switches 37 are shown in FIG. 1 as being provided separately from the source amplifiers 35, the source amplifiers 35 themselves may incorporate the function of the switches 37.
An exemplary operation of the LCD panel driver of FIG. 1 will be explained below with reference to FIG. 2. In FIG. 2, the top three waveforms denoted by the symbols (a), (b) and (c) are the waveforms of the control signals SCA, SCB and SCC. When the control signal SCA is set to “H”, the source drive circuit 30 implements the “source amplifier drive”, allowing the source amplifiers 35 to drive the liquid crystal elements CL within the selected pixels on the LCD panel.
This is followed by setting the control signal SCB to “H” and setting the control signal SCA to “L”. When the control signal SCB is set to “H”, the source drive circuit 30 implements the “gamma resistor direct drive”, allowing the decoder circuit 33 to be directly connected to the liquid crystal elements CL within the selected pixels.
Subsequently, the control signal SCC is set to “H” and the control signal SCB is set to “L”. When the control signal SCC is set to “H”, the source outputs SOUT of the source drive circuit 30 are set to high-impedance. It should be noted that the cycles of the control signals SCA, SCB and SCC may differ depending on the configuration of the liquid crystal display panel.
The boosting clock CLK supplied to the booster circuit 8 does not need to be synchronized with the control signals SCA, SCB and SCC. In the operation shown in FIG. 2, the boosting clock CLK is generated so that the cycle of the boosting clock CLK is longer than the cycles of the control signals SCA, SCB and SCC as shown in FIG. 2(e).
The output signal ps of the comparator CMP1, as shown in FIG. 2(d), indicates the comparison result of the output monitor voltage mo (indicated as the solid line of FIG. 2(g)) and the reference voltage REF1 (indicated as the broken line of FIG. 2(g)). The output signal ps is set to “L” when the output monitor voltage mo exceeds the reference voltage REF1, and set to “H” otherwise. The comparator CMP1 is designed to have different delays in switching the output signal ps from “L” to “H” and in switching the output signal ps from “H” to “L”; the duration of time to set the output signal ps to “H” after the output monitor voltage mo exceeds the reference voltage REF1 is different from that to set the output signal ps to “L” after the output monitor voltage mo is reduced below the reference voltage REF1. This implies that the comparator CMP1 exhibits hysteresis characteristics.
As shown in FIG. 2(f), the NAND circuit 12 sets the output signal gc thereof to “L”, when the output monitor voltage mo is equal to or less than the reference voltage REF1 with the boosting clock CLK pulled up to “H”. In response to the output signal gc being set to “L”, electric charges charged across the boost capacitor C1 are transferred through the transistor T14 to the source drive circuit 30 and other circuits (including the NOT circuit 11, the NAND circuit 12, and the level shift circuit 14), to thereby charge the smoothing capacitor C3. When the boosted power supply voltage VDC2 is increased and the output monitor voltage mo exceeds the reference voltage REF1, the output signal ps of the comparator CMP1 is set to “L” as shown in FIG. 2(d), to fix the output signal gc of the NAND circuit 12 to “H”. In response to the output signal gc being set to “H”, the transistor T14 is turned off. In this state, the voltage level of the boosted power supply voltage VDC2 is maintained by the smoothing capacitor C3, allowing the boosted power supply voltage VDC2 to be gradually decreased. As shown in FIG. 2(g), when the power consumption of circuits operating on the boosted power supply voltage VDC2 (including the source drive circuit 30) is large enough to reduce the output monitor voltage mo down to or less than the reference voltage REF1 while the boosting clock signal CLK maintains at “H”, the output signal ps of the comparator CMP1 is set to “H” as shown in FIG. 2(d). In response to the output signal ps being set to “H”, the output signal gc of the NAND circuit 12 is set to “L” to allow charging the smoothing capacitor C3 as shown in FIG. 2(f).
In such operation, the boosted power supply voltage VDC2 varies irregularly in accordance with current consumption of the circuits operating on the boosted power supply voltage VDC2, including the source drive circuit 30. Larger current consumption causes the output monitor voltage mo to be reduced down to or less the reference voltage REF1 in a shorter time of period. Moreover, the duration of time required for the output monitor voltage mo to exceed the reference voltage REF1 in charging the smoothing capacitor C3 is longer, when the boosted power supply voltage VDC2 is low at the start of charging the smoothing capacitor C3. The boosted power supply voltage VDC2 is thus prevented from being excessively increased, and the smoothing capacitor C3 is charged when the boosted power supply voltage VDC2 is reduced. That is, the booster circuit 8 performs charge and discharge operations irregularly in accordance with the current consumption of the source drive circuit 30 and other circuits operating on the boosted power supply voltage VDC2.
When the booster circuit 8 repeatedly performs charge and discharge operations, the boosted power supply voltage VDC2 undesirably suffers from ripple resulting from the turn-on-and-off of the transistor 14. The ripple on the boosted power supply voltage VDC2 causes noise on the drive voltages outputted from the source drive circuit 30 through the decoder circuit 33 and the source amplifiers 35. In detail, when the control signal SCA is set to “H” to implement the “source amplifier drive” (see FIG. 2(a)) or when the control signal SCB is set to “H” to implement the “gamma resistor direct drive” (see FIG. 2(b)), the ripple of the boosted power supply voltage VDC2 causes noise observed as horizontal stripes on the LCD panel. The ripple causes significant influence on the displayed image especially in the last portion of the “source amplifier drive period”, and in the “gamma resister direct drive period”, because the currents fed to the selected pixels are reduced after the completion of charging and discharging the liquid crystal elements CL of the selected pixels. Furthermore, the amplitude of ripple generated by the charge pump circuit adapted to pulse skipping is increased substantially in proportion to the voltage level of the input power supply voltage. Accordingly, the ripple of the boosted power supply voltage VDC2 causes significant influences on the display image when the power supply voltage VDC fed to the charge pump circuit 10 is increased.
As thus described, a charge pump circuit adapted to pulse skipping may suffer from the deterioration of the display image quality caused by noise on the outputs of source drive circuit resulting from the operation of the charge pump circuit.